instruction processor
英 [ɪnˈstrʌkʃn ˈprəʊsesə(r)]
美 [ɪnˈstrʌkʃn ˈprɑːsesər]
网络 指令处理器; 指令处理机
双语例句
- In this case, the context listing is generated so that you can clearly see the effect of each instruction being executed by the processor.
此例中生成了context清单，以便您能清楚看到处理器执行每条指令的结果。 - The xsl: apply-templates instruction means that the processor walks through the secondary source and applies templates as it goes along.
apply-templates指令意味着处理器遍历辅助源文档，并在遍历过程中应用这些模板。 - Research and Realization on Analysis Method of Application Features Faced Instruction Set Design of Specific Processor
面向专用处理器指令集设计的应用特征分析方法研究与实现 - Many of the complex functions performed in a single, albeit slow, instruction in a CISC processor may require two, three, or more simpler instructions in a RISC.
许多在一个单一的，虽然缓慢进行，在CISC的处理器指令，可能需要两个，三个或更多的在一个简单的RISC指令的复杂功能。 - Synchronization technology based on invalidation of instruction Cache for multi-core processor
基于指令Cache作废的多核处理器同步技术 - Architecture Design and VLSI Implementation of an Application Specific Instruction Set Security Processor
一种专用指令集安全处理器的架构设计与实现 - To improve the high-efficiency parallel processing performance of data flow instruction of a simultaneous multithreading processor, a7-part distributed reservation architecture is presented.
为提高同时多线程微处理器数据流指令高效并行执行性能，提出一种7个部分组成的分布式保留站结构。 - Emulation: The use of a program that allows one processor to simulate the instruction set of another processor.
仿真：用程式使一个处理机能仿效另一个处理机的指令系统的方法。 - The extension of media instruction on the general processor make the real-time multimedia processing algorithm based on processor possible.
通用处理器媒体指令扩展技术的发展，使得基于处理器的实时媒体处理算法成为可能。 - Instruction supply can influence processor performance greatly.
取指令能力的高低对微处理器的性能有很大影响。 - After learning the rules of the Instruction Set of the processor, design the way to generate pseudo-random instructions and pseudo-verify the design with the help of golden model.
根据微处理器核的指令集特点，设计指令伪随机生成的方法，并利用参考模型对处理器进行伪随机激励验证。 - ASIP ( application specific instruction processor) design methodology in the design of embedded microprocessors can not only satisfy the functionality and performance requirements of embedded systems but also shorten the lead time of embedded microprocessors.
在嵌入式微处理器设计中，采用ASIP（ApplicationSpecificInstructionProcessor）处理器设计方法，可以在满足功能和性能要求的同时，缩短嵌入式微处理器产品的研制时间。 - A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware IP cores and one or more on-chip memories usually provides a good solution.
基于总线互连的由一个或多个指令集处理器核、一个或多个专用硬件IP核、一片或多片片上存储器构成的异质体系结构成为媒体系统芯片的合理选择。 - A dual instruction set ARM processor, which supports a reduced Thumb instruction set with a smaller instruction length in addition to a full instruction set, provides an opportunity for a flexible tradeoff between these requirements.
ARM双指令集处理器，在具备通常的32位ARM指令集基础上，还支持一个缩减的16位Thumb指令集，因而为代码优化提供了多个目标之间折衷的机会。 - In order to meet the demand of Application Specific Instruction Set Processor development and shortened time-to-market, the automatic generation environment of functional simulator has caught more and more attention.
为了满足专用指令集处理器的发展和产品上市时间缩短的需要，功能模拟器的自动生成方法受到越来越多的关注。 - In this design, base operating process for SHA_1 algorithm is created to a custom instruction in 32_bit Nios processor, and SHA_1 algorithm is implemented fast using software.
本设计将SHA1算法中的基本运算过程定制为32位Nios处理器的一个用户指令，以软件的方法在Nios处理器中快速实现了SHA1算法。 - Implementation of SHA_1 Algorithm Based on Custom Instruction of Nios Processor
基于Nios处理器用户指令的SHA1算法的实现 - This paper introduces the principle of interface custom instruction of Nios Processor, and describe the designing process of SHA_1 algorithm in in the Nios Processor.
文章介绍了Nios处理器用户指令的接口原理，并详细描述了在Nios处理器中实现SHA1算法的设计过程。 - Flexible-extended instruction set assures the processor upgrade;
可灵活扩充的指令集为处理器的升级和定制准备了坚实的基础； - The instruction emulator based on specficed processor is to resolve the question.
所以基于特定处理器的指令仿真器解决了这个问题。 - The study and Realization of instruction folding in Java processor
Java处理器中指令合并技术的研究与实现 - To address this problem, this paper proposed a method based on hardware and software co-design technology to design and implement an application specific instruction processor to promote the efficiency of the RSA algorithm.
针对这个问题，本文采用了一种基于软硬件协同设计技术的专用指令处理器的的设计和实现方法，来加速RSA算法的运行效率。 - On this basis, an architecture of the network processor based on the network on chip technology and the very long instruction word processor structure is proposed in this paper.
然后此基础上提出了一种基于片上网络和超长指令字结构的网络处理器体系结构。 - Designing Instruction Set Architecture ( ISA) of the Application Specific Instruction set Processor ( ASIP) is based on deep understanding of the application algorithm, while understanding of the algorithm depends on analyzing related source code.
专用指令集处理器（ASIP）指令集设计一般都基于对应用算法源码的分析。 - Very long instruction word digit signal processor will assign recognition and scheduling of parallel task to compiler, so we need a very ambitious complier to use VLIW DSP well.
超长指令字（VLIW）数字信号处理器将并行任务的识别和调度交给了编译器，因此在利用VLIWDSP的时候需要有一个功能更为强大的编译器。 - Application Specific Instruction set Processor ( ASIP) has been proved to be a success in the field of large-scale digital signal processing, it has met all the requirements of our lab project research.
实验室科研项目中，专用指令集微处理器（ASIP）技术成功的应用于大规模数字信号处理领域，并达到了项目的各项指标。 - A low-cost, high-performance application specific instruction set security processor is proposed in this paper.
本文基于专用指令集架构提出了一种低成本、高性能的安全处理器解决方案，能够适用于各种嵌入式信息安全系统。 - The Application Specific Instruction set Processor ( ASIP), which features the high efficiency of Application Specific Intergrated Circuits ( ASIC) and the flexibility of General Purpose Processor ( GPP), has and will have been popular in video processing domain.
专用指令集处理器具备了专用集成电路的高效性与通用处理器的灵活性，在视频处理领域有着广阔的应用前景。 - This paper mainly introduces optimization technology of image processing algorithm based on the very-long instruction word processor.
文章主要介绍在超长指令字处理器上图像处理算法的优化技术。